As electronic devices get smaller, the components within these devices must get smaller as well. Because of this, there has been an increased demand for the miniaturization of components and greater packaging density. Integrated Circuit (IC) package density is primarily limited by the area available for die mounting and the height of the package. One way of increasing the density is to stack multiple die or packages vertically in an IC package. Stacking multiple die or packages will maximize function and efficiency of the semiconductor package.
Stacked semiconductor packages are different from regular semiconductor packages in that they have land pads on both the top and bottom surfaces of the stacked semiconductor package. Due to the need for additional standoff height on a top surface of the stacked semiconductor package, the solder ball size, and hence pitch on the top surface needs to be rather large so that there is sufficient clearance between the stacked packages. However, the use of a large solder ball size is not feasible for the bottom surface of the stacked semiconductor package since this would lead to a solder ball count which would be fairly low.
Because of the above problem, present stacked packages use a ball pitch of one dimension for the top surface and a ball pitch of a second dimension for the bottom surface. The non-uniform ball pitch causes non-alignment of lands between the top surface and the bottom surface. This makes substrate design more complicated since metal traces will have more complex routings. Furthermore, non-uniform ball pitches require more complicated technologies like via-in pad to be used.
Therefore, a need existed to provide a device and method to overcome the above problem.